1. Field of the Invention
This invention is directed to a method of manufacturing a semiconductor device, and more particularly to a method including the steps of exposing a part of a single-crystal or polycrystalline silicon layer formed on an insulating substrate, depositing a film of metal over said silicon layer and annealing to form silicide of the metal for the purpose of lowering the resistance of the single-crystal or polycrystalline silicon layer which is then used as interconnection wirings or electrodes.
2. Description of the Prior Art
Multiple wiring layers have recently been used to increase the integration density of integrated circuits. Referring to FIG. 1A, there is formed a first wiring 2 of aluminum, for example on an insulating substrate 1. An insulating layer of phospho-silicate-glass (PSG) 3 is formed over the aluminum wiring 2, and a second wiring 4 of aluminum is formed on the PSG layer 3.
In the structure, it is needless to say that aluminum wirings 2 and 4 have a resistance of low value. In the shown structure, however, it is generally observed that the wiring 2 has steps 2', and because of these steps, both the PSG layer 3 and the second wiring 4 tend to be formed with steps 3' and 4' respectively as shown. In such a case, the second wiring 4 is liable to be broken at steps 3' and 4'. And thus, the wiring arrangement of FIG. 1A has a weakness in that the manufacturing yield cannot easily be improved although the value of resistance of aluminum is low.
An attempt to anneal the PSG layer 3 to smooth the steps 3' is not used in this case because, at 500.degree. C., aluminum reacts to the PSG or silicon dioxide with which it is in contact, rendering the aluminum wiring unusable.
To improve the wiring arrangement of FIG. 1A, the aluminum wiring 2 is replaced by a silicon wiring 2a as shown in FIG. 2A. After formation of the PSG layer 3, an annealing at 1,050.degree. C. is carried out for reflowing the PSG as shown in FIG. 2A. Aluminum wiring 4 then formed on the smoothed PSG layer 3. This avoids breaking of the wiring 4 experienced in the FIG. 1A embodiment.
And thus, the wiring arrangement of FIG. 2A results in an improved manufacturing yield, but the value of resistance of silicon wiring 2a is high compared to that of aluminum wiring 2 of FIG. 1A.
The same results are observed at contact holes formed over the electrodes 2b and 2c as shown in FIGS. 1B aND 2B. The aluminum wiring 2b in FIG. 1B is replaced by the silicon wiring 2c in FIG. 2B and the steep edge of PSG layer 3 in FIG. 1B is smoothed in FIG. 2B.
Efforts are being made to maintain a high manufacturing yield while holding down the resistance of multiple wirings to as low as possible.
In the structures shown in FIG. 2A and FIG. 2B, it is known generally that single-crystal silicon wirings are preferable to polycrystalline silicon wirings because the value of resistance of single-crystal silicon is half that of polycrystalline silicon. Furthermore, when the single-crystal silicon is turned into a metal silicide, the value of its resistance is reduced by one order. Formation of silicide wiring can be done simultaneously with the manufacture of other parts of the devide without using a separate and independent process.
Japanese Unexamined Patent Publication NO. 135583 of 1978 published on Nov. 27, 1978 discloses a method of manufacturing an insulated-gate field-effect transistor (IGFET). The method is understood to comprise the steps of: masking with a first mask a thick insulating layer on a silicon substrate to fabricate a gate, source and drain to be followed by an etching, then covering the entire surface of the substrate with a thin insulating material and polycrystalline silicon layer successively; masking with second mask the composite layer of polycrystalline silicon and thin insulating material to remove a part of the composite layer in the region where the source and drain are to be formed, to be followed by an etching; introducing impurity material into the exposed region where the source and drain are to be formed, covering the entire surface with a layer of metal for forming a silicide; forming a silicide on the polycrystalline silicon layer in the gate region to form the gate, and forming a silicide on the silicon in the source and drain forming region to form source and drain contacts, and selectively etching that part of the metal layer that has not been turned into silicide.
FIG. 3 illustrates a structure fabricated by such a method in which 11 denotes a substrate of one conductive type, 12 oxidized layers, 14 and 16 regions doped with impurity material, 15 gate electrode, 17 and 18 interconnection layers, and 19 a metal layer.
According to the disclosed method, an annealing of the structure as shown in FIG. 3 is performed, and the metal layer 19 in contact with silicon is turned into a silicide in a self-alignment fashion, and no reaction is noted in the metal layer 19 that is not in contact with silicon. There is silicide formation only at or near the area over the polycrystalline silicon electrodes 15, 17 and 18 and the surface area S where the metal layer 19 is in contact with the region 14 in the substrate 11.
If the annealing is carried out for a longer period in time for the purpose of silicide formation, the formed silicide will penetrate through the region 14. If this happens, there will be a conductive path between the metal layer 19 and the substrate 11.
Because of this, the annealing for silicide formation must be terminated at an appropriate time according to this method. This means it is difficult to regulate the extent or length of the annealing in the disclosed invention. Besides, the method cannot be repeated with certainty and the resistivity cannot be lowered sufficiently.